The present invention relates generally to semiconductor designs, and more particularly to an interconnect structure for integrated circuits (ICs).
As the semiconductor technology advances into the deep sub-micron realm, structures on an IC chip become ever more crowded. Static random access memory (SRAM) cells, for instance, have become so dense that delivering all the necessary electrical wiring to them becomes increasingly difficult. The contacts from one metal level to another require interconnect structures. In dual damascene metallization processes, a conductive material is filled into etched vias and trenches and its excess is polished off by technology, such as chemical-mechanical-polishing (CMP). The contacts, which are formed by vias filled with conductive materials, provide vertical connection, while trenches, which are also filled with conductive materials, provide lateral pads and lines. The vias are typically the smallest features among the semiconductor structures of an IC that must be resolved by lithography and etching.
The ever-shrinking via contacts pose a great challenge to IC manufacturing due to the limited resolution of the photolithography technology. If a misalignment of vias happens, the whole interconnect structure may fail. Thus, as ICs continue to shrink in size, it is of paramount importance to provide an interconnect structure that has a proper alignment margin for the vias.